The Production Planning Challenge
Semiconductor production planning is among the most complex scheduling problems in manufacturing, as Gartner's semiconductor research has consistently noted. A modern fab has 400+ tool types, processes hundreds of products simultaneously, and must balance throughput, cycle time, and yield across thousands of lots competing for shared resources.
Add assembly and test operations --- often at external OSAT facilities on different continents --- and the planning complexity multiplies. End-to-end semiconductor production planning requires coordinating four distinct manufacturing phases with different constraints, cycle times, and optimization criteria.
Phase 1: Wafer Fabrication Planning
Capacity Planning
Fab capacity is measured in wafer starts per week, but the constraint is rarely total starts --- it is specific bottleneck tools. Lithography scanners, typically the most expensive tools in the fab at $150-300M each, usually define capacity limits.
Production planning must balance:
- Product mix — different products require different numbers of lithography passes
- Technology mix — advanced nodes require more layers and process steps than mature nodes
- Engineering lots — R&D wafers consume capacity alongside production
- Maintenance windows — scheduled and unscheduled tool downtime
WIP Management
Work-in-progress in a semiconductor fab can represent $50-200M in value at any given time. Effective WIP management requires:
- WIP targets by operation — maintaining buffer at bottleneck tools to prevent starvation
- Lot priority management — hot lots for urgent customer needs, standard lots for regular production
- Batch optimization — grouping lots for furnace and wet bench operations to maximize throughput
- Rework management — scheduling rework lots without disrupting mainline production
Dispatch and Scheduling
Real-time dispatch decisions determine which lot runs next on each tool. FlowSense Semiconductor provides AI-powered dispatch optimization that considers:
- Lot priority and due date
- Tool qualification status for each product
- Setup time minimization
- Downstream constraint awareness
- Preventive maintenance schedules
Phase 2: Wafer Sort Planning
After fabrication, wafers undergo electrical testing (wafer sort) to identify good die:
- Probe card availability — specific probe cards for each product type
- Tester allocation — balancing tester capacity across products and test programs
- Temperature requirements — some products require hot, cold, or multi-temperature testing
- Yield-based scheduling — prioritizing high-yield lots for early sort to meet delivery commitments
Sort data feeds directly into packaging planning, as the number of good die per wafer determines assembly volume. For a deeper look at how inventory flows between stages, see our semiconductor inventory management guide.
Phase 3: Assembly Planning
Semiconductor assembly (packaging) transforms individual die into packaged ICs:
- Die preparation — backgrinding, dicing, die attach
- Wire bonding or flip chip — connecting die to package substrate
- Encapsulation — molding compound or underfill application
- Marking — laser marking package with identification
Assembly planning must coordinate:
- Die supply from sort — matching die availability with assembly capacity
- Package material availability — substrates, lead frames, bonding wire, mold compound
- Equipment qualifications — not all lines can run all package types
- OSAT capacity allocation — when assembly is outsourced
Phase 4: Final Test Planning
Packaged parts undergo final test before shipment:
- Handler and tester matching — specific handlers for each package type, specific test programs for each product
- Test time optimization — balancing test coverage with throughput
- Binning — classifying parts by performance grade
- Burn-in — stress testing for high-reliability applications
Final test is often the throughput bottleneck for new products, as test programs may not be fully optimized at production launch.
Cycle Time Management
Cycle time in semiconductor manufacturing follows Little's Law: WIP = Throughput x Cycle Time. This deceptively simple equation governs every planning decision in the fab. If a fab targets 5,000 wafer outs per week with an average cycle time of 10 weeks, steady-state WIP must be approximately 50,000 wafers. Increasing throughput without reducing WIP proportionally will extend cycle time, and vice versa.
Fabs track two key metrics: raw processing time (RPT) --- the sum of actual process, metrology, and transport times with zero queuing --- and actual cycle time. The ratio of actual to RPT is the cycle time factor (CTF), sometimes called the X-factor. A world-class fab operates at 2.0-2.5x; many fabs run at 3.0-4.0x, meaning lots spend 60-75% of their time waiting in queue rather than being processed. Reducing CTF from 3.5x to 2.5x on a 10-week nominal cycle time recovers nearly 3 weeks, directly improving delivery lead times and reducing WIP carrying costs.
The ERP tracks cycle time by product, technology node, priority level, and time period. When actual cycle time deviates from target, the system identifies which operations are contributing the most queue time. This analysis often reveals that 80% of excess cycle time comes from 10-15% of operations --- typically lithography queue, furnace batching delays, or metrology bottlenecks. Targeted capacity additions or scheduling rule changes at these specific operations can reduce overall cycle time without broad capital investment. Cycle time improvements also directly benefit yield management, as shorter fab dwell times reduce contamination risk and improve defect densities.
Line Balance and Bottleneck Management
Eli Goldratt's Theory of Constraints (TOC) applies directly to semiconductor fab management, though the implementation is more complex than in discrete manufacturing due to re-entrant process flows --- the same tool set is visited multiple times by the same lot as it progresses through different layers.
Drum-Buffer-Rope (DBR) scheduling adapts to the fab environment as follows. The drum is the bottleneck tool group --- typically advanced lithography scanners, but it shifts dynamically based on product mix and tool availability. The drum sets the pace for the entire fab; its throughput rate defines maximum fab output. The buffer is the WIP queue maintained upstream of the bottleneck, sized to ensure the bottleneck never starves even when upstream tools experience unexpected downtime. Buffer sizing follows statistical analysis: enough to cover 95th-percentile upstream disruption duration, but not so much that it inflates cycle time. The rope is the wafer start rate, throttled to match bottleneck throughput plus a small margin for yield loss and scrap. Starting wafers faster than the bottleneck can process them only increases WIP, cycle time, and fab congestion without improving output.
In practice, the bottleneck in a semiconductor fab is not static. A lithography scanner going down for unscheduled maintenance shifts the constraint temporarily to etch or deposition. The ERP must recalculate line balance dynamically, adjusting dispatch priorities across all tool groups to maximize throughput at the current constraint. FlowSense Semiconductor performs this rebalancing in real time, using equipment status feeds and WIP position data to identify the active constraint and adjust dispatch rules within minutes of a status change.
Integrated Planning Across Phases
As SEMI's manufacturing best practices highlight, the real challenge is coordinating these four phases into a coherent plan. When a fab excursion delays 50 lots by two weeks, the ripple effect propagates through sort, assembly, and test, potentially affecting dozens of customer deliveries.
Integrated production planning provides:
End-to-End Visibility
A single planning system showing WIP status, capacity utilization, and delivery projections across all four phases. Planners see the complete picture rather than optimizing each phase independently.
Constraint Propagation
When a constraint in one phase is identified, the system automatically evaluates the impact on downstream phases. A tester breakdown in final test triggers replanning of sort priorities to avoid building excess die inventory.
What-If Analysis
Planners simulate scenarios before committing:
- What if we add a third shift in assembly?
- What if we expedite these 20 lots through fab?
- What if the customer moves their delivery date forward by two weeks?
- What if we divert 10% of tester capacity to a new product qualification?
Consider a concrete scenario: a major automotive customer requests a 20% volume increase for a safety-critical microcontroller, effective in 8 weeks. The what-if engine evaluates the request across all four phases simultaneously. In fab, it checks whether the bottleneck lithography tool group has sufficient uncommitted capacity for the additional wafer starts, factoring in current product mix and scheduled maintenance windows. If lithography is at 94% utilization, the system calculates that accommodating the increase requires either deferring 200 wafer starts of a lower-priority product or adding weekend maintenance shifts to recover 3% utilization. At wafer sort, it verifies probe card availability and tester hours for the specific test program. In assembly, it checks substrate and lead frame inventory against the inventory management system and flags that current substrate stock covers only 12 weeks at the new rate, requiring an expedited purchase order to the substrate supplier with a 6-week lead time. At final test, it identifies that the burn-in ovens are the constraint, operating at 91% utilization, and the volume increase would push utilization above the 95% threshold that historically causes scheduling conflicts. The system presents all of these findings in a single impact report with options: accept with substrate expedite fee and lower-priority product deferral, partially accept at 10% increase within current constraints, or negotiate a 12-week ramp instead of 8 weeks. This analysis, which would take a planning team days to compile manually, is available in minutes.
Automated Replanning
When actual performance deviates from plan, the system automatically adjusts downstream schedules and alerts affected stakeholders. This replanning happens continuously, not in weekly planning meetings.
Best Practices for Semiconductor Production Planning
- 1Plan at the constraint — identify and manage the bottleneck at each phase
- 2Maintain strategic WIP buffers — protect bottleneck utilization with upstream inventory
- 3Integrate external operations — include OSAT capacity and lead times in the plan
- 4Update frequently — semiconductor production is too dynamic for weekly static plans
- 5Measure plan adherence — track how actual execution compares to plan and improve the planning model
Coordinate production across all four phases. See FlowSense Semiconductor's planning tools.
